Asynchronous communications element

摘要: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The includes a shift register receives serial data transfers from station, FIFO parallel the for transfer CPU, station. A time delay eliminates multiple interrupts "empty" condition that has already been indicated CPU. Programmable levels on FIFO, together with continues fill beyond programmed level, allow adjustments variable latency times. indicates there are characters in have not reached programmable trigger but exceed specified limit conditions. may be individually simultaneously disabled; single-bit flag their status.