HPEX: A Hierarchical Parasitic Circuit Extractor

摘要: A hierarchical parasitic circuit extractor HPEX for Manhattan layouts is described. can model interconnection lines as distributed lumped circuits directly from a layout by using analytical formulas instead of numerical methods. The difference in feature sizes between mask and actual fabricated conductors also taken into account geometrical preprocessing algorithm based on novel Y-X scanline method simple rectangle data structure. In addition, accurate node reduction technique the concept Elmore's delay employed to make verification simpler. All features mentioned above clearly indicate that will be promising tool verifying VLSI system performance especially when interconnect parasitics associated with are consideration.