摘要: We have implemented a fast hierarchical circuit extractor for the Magic VLSI layout system. The keys to its speed are new algorithm based on corner-stitching, and ability extract cells incrementally. Because is incremental, typically only few must be re-extracted when changes. computes connectivity transistor dimensions, both internodal substrate parasitic capacitance, resistances. It parameterized work across wide range of MOS technologies.
acm.org
sci-hub.st 参考文章(11)
B. J. Nelson, M. Shand, An integrated, technology-independent, high-performance artwork analyzer for VLSI circuit design Journal of VLSI and computer systems. ,vol. 1, pp. 271- 295 ,(1985)
Anoop Gupta, ACE: A Circuit Extractor design automation conference. pp. 721- 725 ,(1983) , 10.5555/800032.800751
J.K. Ousterhout, Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 3, pp. 87- 100 ,(1984) , 10.1109/TCAD.1984.1270061
William J. Herman, Gary M. Tarolli, Hierarchical Circuit Extraction with Detailed Parasitic Capacitance design automation conference. pp. 337- 345 ,(1983) , 10.5555/800032.800686
David Ungar, Ricki Blau, Peter Foley, Dain Samples, David Patterson, Architecture of SOAR: Smalltalk on a RISC international symposium on computer architecture. ,vol. 12, pp. 188- 197 ,(1984) , 10.1145/773453.808182
Neil Weste, Virtual grid symbolic layout ACM SIGDA Newsletter. ,vol. 12, pp. 2- 10 ,(1982) , 10.1145/382096.382098
John K. Ousterhout, Switch-Level Delay Models for Digital MOS VLSI design automation conference. pp. 489- 495 ,(1984) , 10.5555/800033.800851
Steven P. McCormick, EXCL: A Circuit Extractor for IC Designs design automation conference. pp. 616- 623 ,(1984) , 10.5555/800033.800863
John K. Ousterhout, Gordon T. Hamachi, Walter S. Scott, Robert N. Mayo, George S. Taylor, Magic: A VLSI Layout System design automation conference. pp. 152- 159 ,(1984) , 10.5555/800033.800790
M. Ellement, C. E. Huang, P. J. Fowler, J. D. Bastian, L. P. McNamee, Symbolic Parasitic Extractor for Circuit Simulation (SPECS) design automation conference. pp. 346- 352 ,(1983) , 10.5555/800032.800687