作者: A. J. van Genderen , N. P. van der Meijs
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摘要: In this paper, we describe how have improved the efficiency of a finite-element method for interconnect resistance extraction by introducing articulation nodes in finite element mesh. The are found detecting equipotential regions and lines interconnects. Without generating inaccuracies, these split mesh into small pieces that can be solved independently. has been implemented layout-to-circuit extractor Space. All resistances circuit containing 63,000 transistors extracted on an HP 9000/735 workstation approximately 70 minutes.