作者: Akil K. Sutton , Marco Bellini , John D. Cressler , Jonathon A. Pellish , Robert A. Reed
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摘要: We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from sub-collector substrate junction. n-ring affects neither DC nor AC performance HBT and does not compromise its inherent multi-Mrad TID tolerance. effects ion strike location angle incidence, as well placement, area, bias collection are investigated experimentally using a 36 MeV O2 microbeam. results indicate that shunting through can result up 90% reduction collector collected strikes outside DT 18% emitter center. 3-D transient simulations NanoTCAD used verify experimental observations, shed insight into underlying physical mechanisms. Circuit implications this RHBD technique discussed recommendations made.