Design and VHDL modeling of all-digital PLLs
作者： E. Zianbetov , M. Javidan , F. Anceau , D. Galayko , E. Colinet
DOI: 10.1109/NEWCAS.2010.5603947
关键词:
摘要: In this paper, a VHDL model of second-order all-digital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL destined to be part distributed clock generators networks the ADPLL. paper presents an original and architecture digital multi-bit phase-frequency detector (PFD), describes in details modeling metastability issues related with asynchronous operation PFD. This particular PHD required by synchronised network context generator. whole have been validated purely behavioral (VHDL) mixed simulation, which PFD was represented its transistor-level model.
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