Approximation-aware testing for approximate circuits

摘要: A wide range of applications significantly benefit from the Approximate Computing (AC) paradigm in terms speed or power reduction. AC achieves this by tolerating errors design. These are introduced into design either manually designer approximate synthesis approaches. From here, standard flow is taken. Hence, manufactured chip eventually tested for production using well established fault models. To be precise, if test a pattern fails, sorted out. However, general perspective procedure results throwing away chips which perfectly fine taking account that considered (i.e. physical defect leads to error) can still tolerated because approximation. This lead significant amount yield loss. In paper, we present an approximation-aware methodology easily integrated regular flow. It based on pre-process identify approximation-redundant faults. By this, remove all potential faults no longer need they under given error metric. Our experimental and case studies variety benchmark circuits show improvement.