Porosity aware buffered steiner tree construction

摘要: In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs be performed thousands of nets within an integrated physical synthesis system. Modern designs may contain large blocks which severely constrain the locations. Even when there appear space for buffers in alleys between blocks, these regions are often densely packed or needed later fix critical paths. Therefore, synthesis, a scheme aware porosity existing layout able decide insert dense performance improvement and utilize sparser chip.This work addresses problem finding porosity-aware buffering solutions by constructing "smart Steiner tree" pass van Ginneken's topology based algorithm. This flow allows one fully integrate algorithm into system without paying exorbitant runtime penalty. We show that significant improvements obtained this approach is