Efficient Hardware Barrier Synchronization in Many-Core CMPs

摘要: Traditional software-based barrier implementations for shared memory parallel machines tend to produce hotspots in terms of and network contention as the number processors increases. This could limit their applicability future many-core CMPs which possibly several dozens cores would need be synchronized efficiently. In this work, we develop GBarrier, a hardware-based mechanism especially aimed at providing efficient barriers CMPs. Our proposal deploys dedicated G-line-based allow fast signaling arrival departure. Since GBarrier does not have any influence on system, avoid all coherence activity barrier-related traffic that traditional approaches introduce restrict scalability. Through detailed simulations 32-core CMP, compare against one most set kernels scientific applications. Evaluation results show average reductions 54 21 percent execution time, 53 18 traffic, also 76 31 energy-delay2 product metric full CMP when applications, respectively, are considered.