Method for automaticallly remapping an HDL netlist to provide compatibility with pre-synthesis behavioral test benches
作者： Andrew Maurice Bloom , Rodrigo Jose Escoto
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摘要: A computer implemented apparatus and method that automates the entry, modification, analysis, generation of test benches from electrical circuits, both which are specified as hardware description language (HDL) files. The implemented-method also provides a unique mechanism blends entry display timing requirements must be met by electric circuit.
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