High-speed serial data signal interface circuitry with multi-data-rate switching capability
作者： Sergey Shumarayev , Weiqi Ding , Wilson Wong , Thungoc M. Tran , Allen Chan
DOI:
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摘要: High-speed serial data signal transmitter and/or receiver circuitry is able to dynamically switch between handling at two (or more) different rates. Such a can be made very rapidly and with no requirement for reprogramming or reconfiguring the circuitry. Circuitry glitchlessly switching clock signals having frequencies also provided may used in above-mentioned
lens.org 参考文章(8)
Sudhaker Reddy Anumula, Paul Vanderbilt, Wei Fu, Mehmet Mustafa Eker, Joseph J. Balardeta, Configurable triple phase-locked loop circuit and method ,(2002)
Donald A. Bradley, Dual modulus fractional divider ,(1988)
Nasser A. Kurd, Javed S. Barkatullah, PLL with controlled VCO bias ,(2005)
Ramanand Venkata, Rakesh H Patel, Chong H Lee, Multiple data rates in programmable logic device serial interface ,(2005)
Chen-Chih Huang, Chao-Cheng Lee, Dual phase-locked loop clock synthesizer ,(1996)
Jeffrey Sanders, PLL circuit with self-selecting variable divide ratio ,(2005)
Sergey Shumarayev, Wilson Wong, Thungoc M. Tran, Tim Tri Hoang, High-speed serial data signal interface architectures for programmable logic devices ,(2007)
Sergey Shumarayev, Weiqi Ding, Wilson Wong, Allen Chan, Transmitter with multiple phase locked loops ,(2008)