Slotless module-based reconfiguration of embedded FPGAs

摘要: The difficult aspect of hardware reconfiguration is not creating the computational blocks, which are generally available from FPGA vendors and third parties, but linking blocks in a manner that suits each application's unique connectivity, bandwidth, latency requirements. Our approach uses standard Xilinx implementation tools to generate dynamic module partial bitstreams, choosing module's coordinates completing connections other modules runtime operations. Scripts automatically add interface wrappers library relocatable bitstreams. used by an efficient system completes application requests for instancing connecting modules, effectively insulating designer complexities. In this way, large sandbox may be allocated rather than fixed slots interconnect. Application engineers interact with Wires on Demand (WoD) through software API, do have master description languages tools.