Dynamic partial reconfi guration for pipelined digital systems— A Case study using a color space conversion engine

摘要: In digital hardware design, reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) allow for a unique feature called partial reconfiguration (PR). This refers to the reprogramming of subset logic during active operation. PR allows multiple blocks be consolidated into single partition, which can reprogrammed at run-time desired. may reduce circuit (and silicon area) requirements and greatly extend functionality. Furthermore, dynamic (DPR) that does not halt system reprogramming. configuration overlap with normal processing, potentially achieving better performance than static (halting) implementation. work has investigated advantages trade-offs DPR applied an existing color space conversion (CSC) engine provided by Hewlett-Packard (HP). Two versions were created: single-pipeline engine, only tasks in specific sequences; dual-pipeline any consecutive tasks. These implemented Virtex-6 FPGA. Data communication occurs over PCI Express (PCIe) interface. Test results show improvements execution speed resource utilization, though some are minor due intrinsic characteristics CSC pipeline. The version outperformed most test cases. Therefore, future will focus on multiple-pipeline architectures.