Accelerating FPGA development through the automatic parallel application of standard implementation tools

摘要: FPGA implementation tool turnaround time has unfortunately not kept pace with density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. As in many multithreaded applications, communication and synchronization incur significant overheads. Even if these challenges are overcome, the large graph data structures used can quickly exhaust memory bandwidth as more cores employed. We approach problem a different way for development environments which some circuit speed area optimization may be sacrificed improved debug turnaround. The PATIS automatic floorplanner enables dynamic modular design. While existing incremental flows facilitate timing closure late design cycle by reusing layout unmodified blocks, accelerates non-local changes physical arising from exploration addition circuitry. A floorplan consists partial modules structured interfaces observable through configuration readback, allowing module ports passively probed disturbing layout. Although supports design, global still rapid because each block's bitstream produced independent concurrent invocations standard Xilinx tools running on separate hosts. continuous background task proactively generates variants further accelerate changes.