Power up/power down controller and power fail detector for processor

摘要: A power fail control system for a CPU (10) and external memory (16) utilizes controller (18). The (18) is operable to detect an early situation output interrupt the (10). then goes into down sequence stores critical instructions in internal array (30) constituting hidden during sequence. An out of tolerance detector detects when supply voltage has fallen below predetermined threshold generates reset signal. signal input indicate that no further are executable. In addition, Chip Enable switch (46) operated inhibit signals from being transferred (16). also inhibited having data written thereto presence backup battery (22) provided which connected one side switch. other voltage. When falls voltage, current