On Power and Performance Tradeof f of L2 Cache Compression
作者： Tom Chen , Chandrika Jena , Tim Mason
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摘要: This paper presents the power-performance trade off of three different cache compression algorithms. Cache im- proves performance, since compressed data increases effective capacity by reducing misses. The unused memory cells can be put into sleep mode to save static power. increased perfor- mance and saved power due must more than delay consumption added CODEC(COmpressor DECompressor) block respectively. Among studied algorithms, power- characteristic Frequent Pattern compression(FPC) is found most suitable for compression.
参考文章(10)
L. Benini, D. Bruni, A. Macii, E. Macii, Hardware implementation of data compression algorithms for memory energy optimization ieee computer society annual symposium on vlsi. pp. 250- 251 ,(2003) , 10.1109/ISVLSI.2003.1183487
H. Rahman, C. Chakrabarti, A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage international symposium on circuits and systems. ,vol. 2, pp. 297- 300 ,(2004) , 10.1109/ISCAS.2004.1329267
Alaa R. Alameldeen, David A. Wood, Adaptive Cache Compression for High-Performance Processors ACM SIGARCH Computer Architecture News. ,vol. 32, pp. 212- 223 ,(2004) , 10.1145/1028176.1006719
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan, Sleep transistor sizing using timing criticality and temporal currents Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05. ,vol. 2, pp. 1094- 1097 ,(2005) , 10.1145/1120725.1120832
S. Bobba, I.N. Hajj, Maximum leakage power estimation for CMOS circuits Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design. pp. 116- 124 ,(1999) , 10.1109/LPD.1999.750412
James Kao, Siva Narendra, Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques international conference on computer aided design. pp. 141- 148 ,(2002) , 10.1145/774572.774593
M. Kjelso, M. Gooch, S. Jones, Design and performance of a main memory hardware data compressor Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies. pp. 423- 430 ,(1996) , 10.1109/EURMIC.1996.546466
Alberto Macii, Enrico Macii, Roberto Zafalon, Fabrizio Crudo, A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors design, automation, and test in europe. pp. 10024- 10029 ,(2003) , 10.5555/789083.1022700
J.W. Tschanz, S.G. Narendra, Yibin Ye, B.A. Bloechel, S. Borkar, Vivek De, Dynamic-sleep transistor and body bias for active leakage power control of microprocessors international solid-state circuits conference. ,vol. 38, pp. 1838- 1845 ,(2003) , 10.1109/JSSC.2003.818291
Changbo Long, Lei He, Distributed sleep transistor network for power reduction Proceedings of the 40th conference on Design automation - DAC '03. pp. 181- 186 ,(2003) , 10.1145/775832.775879