Hardware implementation of data compression algorithms for memory energy optimization

摘要: This paper describes implementation details of a hardware compression and decompression unit (CDU) for optimizing energy consumption in processor-based systems. Many algorithms data (i.e., profile-driven, adaptive, differential) have previously been introduced. In all cases, are performed on-the-fly on the cache-to-memory path: Uncompressed cache fines compressed before they written back to main memory, decompressed when refills occur. completes extends these previous contributions by providing evidence feasibility proposed architectures specifically addressing issues. CDU design is targeted towards minimization cache-bus-memory subsystem with strict constraint performance. As result, average memory reductions evaluated several benchmark programs around 24%, at no performance penalty.