Nanoscale floating gate and methods of formation
作者： D. V. Nirmal Ramaswamy , Gurtej S. Sandhu
DOI:
关键词:
摘要: A memory cell is provided including a tunnel dielectric layer overlying semiconductor substrate. The also includes floating gate having first portion the and second in form of nanorod extending from portion. In addition, control separated by an intergate layer.
google.co.uk 参考文章(54)
Heather Hudspeth, Joleyn Balch, Anping Zhang, Reed Corderman, Loucas Tsakalakos, Gated nanorod field emitters ,(2005)
Sripao Nagarao, Elgin Kiok Quek, Dong Sohn, Lee Teo, Synthesis of GE nanocrystal memory cell and using a block layer to control oxidation kinetics ,(2005)
David L. O'Meara, Michael Alan Sadd, Bo Jiang, Sucharita Madhukar, Ramachandran Muralidhar, Srikanth B. Samavedam, Bruce E. White, Memory cell and method for programming thereof ,(2000)
Paul J. Rudeck, Gate coupling in floating-gate memory cells ,(2004)
Udayan Ganguly, Yuegang Zhang, Edwin Kan, Nanotube- and nanocrystal-based non-volatile memory ,(2005)
Ramachandran Muralidhar, Michael A. Sadd, Rajesh A. Rao, Bruce E. White, Nanocrystal non-volatile memory cell and method therefor ,(2006)
Mun-Cheol Paek, Sung-Yool Choi, Jeen Hur, Gi-Pyung Han, Kyoung-Ik Cho, Triode-type field emission device having field emitter composed of emitter tips with diameter of nanometers and method for fabricating the same ,(1999)
Po-Tsun Liu, Simon-M Sze, Shuo-Ting Yan, Tsung-Ming Tsai, Ya-Hsiang Tai, Ting-Chang Chang, Chi-Wen Chen, Non-volatile memory and method of manufacturing floating gate ,(2006)
Gurtej S. Sandhu, Chandra Mouli, Reduced leakage memory cells ,(2006)
Eric Blomiley, Cem Basceri, Gurtej Sandhu, Nirmal Ramaswamy, Forming a vertical transistor ,(2005)