作者: Suresh N. Rajan
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摘要: A memory device comprises a first and second integrated circuit dies. The die core as well interface circuit. permits full access to the cells (e.g., reading, writing, activating, pre-charging refreshing operations cells). that interfaces core, via circuit, an external bus, such synchronous bus. technique combines dies with configure device. speed test on is conducted, electrically coupled based of die.