作者: Chih-Hsin Wang
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摘要: A method of forming an array floating gate memory cells, and formed thereby, wherein each cell includes electrical conductive in a trench semiconductor substrate, control having portion disposed over insulated from the gate. An tunneling is by insulating layer to form tri-layer structure permitting both electron hole charges through at similar rate. Spaced apart source drain regions are with region adjacent lower gate, upper channel therebetween along sidewall trench.