Interconnect design with controlled inductance
作者： Quat T. Vu , Ling-Chu Chien
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摘要: An integrated circuit device interconnect with controlled inductance. includes an insulating layer (25) formed on a substrate and (21) disposed the extending along first path. A dedicated current return path (22) having one end configured to be coupled ground is parallel (21), such that signal received by returned via when ground. Inductance of thus reducing area loop (27) (22). In embodiment, (32) in embedded plane (34) just above or below (41). this (41) (46) together act as built-in decoupling capacitor, further offsetting inductive time constant approach critical damping.
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