Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs

摘要: Energy and reliability optimization are two of the most critical objectives for synthesis multiprocessor systems-on-chip (MPSoCs). Task mapping has shown significant promise as a low cost solution in achieving these standalone or tandem well. This paper proposes multi-objective design space exploration to determine tasks an application on system voltage/frequency level each (exploiting DVFS capabilities modern processors) such that platform is improved while fulfilling energy budget performance constraint set by designers. In this respect, given MPSoC incorporates not only impact voltage frequency aging processors (wear-out effect) but also susceptibility soft-errors -- joint consideration missing all existing works domain. Further, proposed soft-error tolerance selective replication tasks, making approach interesting blend reactive proactive fault-tolerance. The combined objective minimizing core together with transient faults under performance/energy solved using genetic algorithm exploiting tasks' mapping, tuning knobs. Experiments conducted real-life synthetic graphs clearly demonstrate advantage approach.