Reliability-Driven System-Level Synthesis of Embedded Systems
作者： Cristiana Bolchini , Antonio Miele
DOI: 10.1109/DFT.2010.11
关键词:
摘要: This paper proposes an enhanced system-level synthesis flow for the design of reliable embedded systems, extending classical process to introduce fault mitigation properties in under consideration. The strategy first explores adoption hardening techniques that, given initial task graph and user's reliability requirements, redundancies mapping constraints on available resources, which possibly expose detection/tolerance features. reliability-aware is then implemented by means a scheduling approach thus obtaining hardened implementation. Experimental results are reported support validity proposal.
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