Dynamic simulation of migration induced failure mechanism in integrated circuit interconnects

摘要: Abstract At the moment miniaturisation of integrated circuits for consumer electronics means to decrease size Cu interconnects below 100 nm, while a lifetime 3–5 years has be guaranteed. For industrial and automotive applications wider Al (∼350 nm) are used, but an extreme low rate failures (0.1 ppm) reached produce reliable end-products including dozens components. A further progress in development high-end more complex products needs better prediction possible failure mechanism related time chosen technology. This investigation is focused on migration induced void formation combines results process simulations, back end line, (intrinsic pre-stress) with dynamic simulation material movement interconnects. To minimise gap between idealized simulations reliability tests grain structure lines, interaction electromigration mass flux due concentration gradients, as well different transport boundary interface diffusion were taken into account. surrounding metal existing voids specific activation energies dependence crystal orientation surfaces given. As result point will given back-end technologies.