Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations

摘要: Described is a finite impulse filter response (FIR) for use by signal processors. A demultiplexer receives input data samples at an rate. The FIR includes plurality of computational units arranged in systolic array taps and phases. Each unit operates clock rate that slower than the During each cycle, phases produce output provides equal to filters can thus support although exceeds maximum speed processor. also operate reduced speed, while continuing rate, increase power efficiency