DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof

作者: Hiroshi Nakamura

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摘要: An upper electrode of a capacitor is structured to have its end surface recessed from an interlayer insulating layer covering said layer, at position where the faces bit line contact portion. The and first are patterned same shape. Subsequently, only side etched recedes by isotropic etching. receding covered with sidewall layer. portion or pad for formed along thick amount Thus, distance between increased, therefore dielectric breakdown voltage therebetween also increased.

参考文章(4)
Gernia Tang, Gary A. Pors, DRAM memory cell with tapered capacitor electrodes ,(1990)
Hideo Sunami, Yoshifumi Kawamoto, Toru Kaga, Shinichiro Kimura, Semiconductor memory having stacked capacitor ,(1990)