Conductive channel pseudo block process and circuit to inhibit reverse engineering
作者： James P. Baukus , Gavin J. Harbison , Lap-Wai Chow , William M. Clark
DOI:
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摘要: A technique for and structures camouflaging an integrated circuit structure. The structure is formed by a plurality of layers material having controlled outline. layer conductive outline disposed among said to provide artifact edges the that resemble one type transistor (operable vs. non-operable), when in fact another was used.
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