作者: C. Michael , M. Ismail
DOI: 10.1109/4.127338
关键词:
摘要: A generalized parameter-level statistical model, called MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated preserve the inherent correlations between parameters while accounting for dependence variance on device separation distance area. Using a Monte Carlo approach to sampling, circuit output means standard deviations can be simulated. Incorporated in CAD environment, these modeling algorithms will provide analog designer with method determine effect both layout sizing variance. Test chips have been fabricated two different fabrication processes extract information required by model. Experimental simulation results subcircuits are compared verify algorithms. >