Method of making planarized EPROM array
作者： Howard L. Tigelaar
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摘要: An array of floating gate memory cells is formed at a face semiconductor layer (10). The includes plurality elongate spaced-apart parallel source/drain regions (12). A thick dielectric (14) on the face. orifices (16) are through to face, each orifice exposing portions two adjacent (12) and extending therebetween. thin first insulators (18) in (16). Next, conductive electrodes (20) (18), with combined thickness electrode insulator approximating (14). planarized surface thus presented for deposition an interlevel (22, 24) control (26).
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