Cellular array processor with individual cell-level data-dependent cell control and multiport input memory

摘要: In an array of processing cells arranged as a single instruction multiple data processor, each cell contains logic which enables the to determine individually whether it will perform arithmetic or operation be in idle condition. This cell-level includes control register whose contents operating condition cell, and also PUSH/POP/COMPLEMENT stack mechanisms represent complex levels conditions, load results test into register, providing data-dependent at level.