Method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated circuitry
作者： Wendell P. Noble
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Sang H. Dhong, Matthew R. Wordeman, Lewis M. Terman, Wei Hwang, Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors ,(1991)
Chen C. Hsue, Gary Hong, Method of making buried bit line ROM with low bit line resistance ,(1994)
Subhas Bothra, Harlan Lee Sur, Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same ,(1999)
Bor-Yeu Tsaur, Hong-Kyun Choi, Process for making junction field-effect transistors ,(1986)
Chris Wyland, Thermal-conductive substrate package ,(2003)
Klaus D. Beyer, Andrie S. Yapsir, Reach-through isolation silicon-on-insulator device ,(1994)
Zbigniew P. Sobczak, Formation and planarization of silicon-on-insulator structures ,(1985)
Katsuyoshi Washio, Takahiro Onai, Masatada Horiuchi, Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator ,(1996)
P. Bakeman, A. Bergendahl, M. Hakey, D. Horak, S. Luce, B. Pierson, A high performance 16-Mb DRAM technology symposium on vlsi technology. pp. 11- 12 ,(1990) , 10.1109/VLSIT.1990.110983