作者: Peter J. Vigil , Louis S. Lederer , James S. Blomgren
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摘要: A microprocessor die contains several CPU cores that are substantially identical. large second-level cache on the is shared among multiple CPU's. When 3 CPU's die, their outputs compared during a self-testing mode. If from all three match, then no error detected. two but third output mismatches, faulty. The each serial scan-chain shift-out, parity internal test points, and result written to cache. Each core has scan chain. chain strings together most flip-flops in into clock pulsed shift out data these flip-flops. During period, other Internal points within defined at high traffic areas pipeline. Parity generated one for cycle. results back also compared, arbitration allows write while discarded. self-test circuit accumulates errors reports an inexpensive external tester.