摘要: The radio-frequency (RF) potential of logic CMOS is assessed in this paper. Steps towards an optimum RF performance are explained. Devices optimized for the frequency responses (f/sub T/ and f/sub max/), minimum noise figure (F/sub min/), 1/f-noise based on device layout, bias conditions, type gate dielectric. Those steps verified through a detailed study IBM's 0.18 /spl mu/m technology. identification high technology points out advantage over dedicated
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