Adapting cache partitioning algorithms to pseudo-LRU replacement policies

作者: Mateo Valero , Kamil Kedzierski , Miquel Moreto , Francisco J. Cazorla

DOI: 10.1109/IPDPS.2010.5470352

关键词:

摘要: Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The algorithms proposed so far assume Least Recently Used (LRU) as the underlying replacement policy. However, it has been true LRU imposes extraordinary complexity area overheads when implemented on high associativity caches, such last level caches. As a consequence, current processors available market use pseudo-LRU policies, which provide similar behavior LRU, while reducing hardware complexity. Thus, presented LRU-based solutions cannot be applied real architectures. This paper proposes complete system for caches using In particular, focuses implementations by Sun Microsystems IBM, called Not (NRU) Binary Tree (BT), respectively. We propose accuracy profiling logic both schemes. evaluate our proposals' costs terms power, compare them against algorithm. Overall, this presents two techniques adapt existing policies. results show impose negligible performance degradation with respect LRU.

参考文章(29)
Dan Connors, Alex Settle, Antonio González, Enric Gibert, A dynamically reconfigurable cache for multithreaded processors Journal of Embedded Computing. ,vol. 2, pp. 221- 233 ,(2006)
Weirong Wang, Aloysius K. Mok, A class-based approach to the composition of real-time software components Journal of Embedded Computing. ,vol. 1, pp. 3- 15 ,(2005) , 10.5555/1233771.1233773
Kevin C. Stelzer, Wen-Tzer Thomas Chen, Peichun Peter Liu, Implementation of a pseudo-LRU algorithm in a partitioned cache ,(2003)
Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, MLP-aware dynamic cache partitioning high performance embedded architectures and compilers. pp. 337- 352 ,(2008) , 10.1007/978-3-540-77560-7_23
G. E. Suh, L. Rudolph, S. Devadas, Dynamic Partitioning of Shared Cache Memory The Journal of Supercomputing. ,vol. 28, pp. 7- 26 ,(2004) , 10.1023/B:SUPE.0000014800.27383.8F
James Donald, Margaret Martonosi, Power efficiency for variation-tolerant multicore processors international symposium on low power electronics and design. pp. 304- 309 ,(2006) , 10.1145/1165573.1165645
M. Moudgill, J.-D. Wellman, J.H. Moreno, Environment for PowerPC microarchitecture exploration IEEE Micro. ,vol. 19, pp. 15- 25 ,(1999) , 10.1109/40.768496
Ravi Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, Srihari Makineni, Don Newell, Yan Solihin, Lisa Hsu, Steve Reinhardt, QoS policies and architecture for cache/memory in CMP platforms measurement and modeling of computer systems. ,vol. 35, pp. 25- 36 ,(2007) , 10.1145/1254882.1254886
Alex Ramirez, F Cazorla, M Moreto, K Nesbit, J Smith, M Valero, Multicore Resource Management IEEE Micro. ,vol. 28, pp. 6- 16 ,(2008) , 10.1109/MM.2008.43