Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)

摘要: A method of deadlock-free, automatic configuration and reconfiguration modules having a two- or multidimensional cell arrangement, in which unit for controlling the manages set associated configurable elements, being subset total all management takes place as follows: requests from elements are sent to unit; processes requests; data command sequence; after has been fully processed, new accepted again, still be loaded existing previous buffer memory (FILMO) into until request occurs.