Memory cell having isolated charge sites and method of fabricating same
作者： Chia-Hong Jan , Walid M. Hafez , Ting Chang
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摘要: Memory cells having isolated charge sites and methods of fabricating memory are described. In an example, a nonvolatile trap device includes substrate channel region, source region drain region. A gate stack is disposed above the substrate, over The tunnel dielectric layer first charge-trapping second regions separated by distance. also isolating between layer. electrode
lens.org 参考文章(15)
Marius Orlowski, Method for making a multibit transistor ,(2006)
Luigi Pascucci, Process for fabricating a dual charge storage location memory cell ,(2001)
Ching-Yuan Wu, Self-aligned multi-bit flash memory cell and its contactless flash memory array ,(2002)
Fu-Chang Hsu, Peter Wung Lee, Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array ,(2008)
Fernando Gonzalez, Francis L. Bensistant, Dual floating gate programmable read only memory cell structure and method for its fabrication and operation ,(2001)
Cheong M. Hong, Chi Nan Brian Li, Ko-Min Chang, Method of forming a semiconductor device and structure thereof ,(2007)
Tazrien Kamal, Chi Chang, Wei Zheng, Memory device having a P+ gate and thin bottom oxide and method of erasing same ,(2003)
Schaijk Robertus T. F. Van, Duuren Michiel J. Van, Vertical split gate non-volatile memory cell and method of fabrication thereof ,(2003)
良裕 加柴, Yoshihiro Kashiba, Masao Yamawaki, Tatsuhiko Ikeda, 正雄 山脇, Kenji Suematsu, 龍彦 池田, 憲治 末松, High-frequency circuit device and its manufacture ,(1995)
Okumura Yoshiki, Shirahata Masayoshi, SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ELECTRICALLY WRITING AND ERASING AND ITS MANUFACTURE AND MEMORY RECOGNITION ,(1995)