Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware

摘要: With the semiconductor industry moving towards smaller and more advanced process nodes, reliability of fabricated system-on-chips (SoCs) has become a significant problem, although it can be mitigated by proper verification validation methodologies. Typical neuromorphic SoC chips are resource constrained have very low power envelopes, pushing designers to forego integration onchip debug circuits. Futhermore, these specialized SoCs may not even capable supporting memory circuits due inclusion novel types. Hence, is huge challenge execute comprehensive system level post-silicon suite on such chips, while aiding debugging efforts reliably. This paper presents methodology algorithm test all neurocores within our custom designed processing unit (NPU) chip, focused pinpointing faults synaptic weight storage elements. The described does require any built-in infer detect faults. Based results, NPU chip was able respond accordingly performed tests under optimal voltage frequency conditions.