Method of forming a logic array for a decoder

摘要: A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional in a array. The transistor field-effect (FET) an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If particular floating charged stored electrons, then the will not turn on act as absence of at this location logic within decoder. decoder programmed test output line responsive bits received via input lines. includes densely packed cells, each cell semiconductor pillar providing shared for two have individual gates distributed opposing sides pillar. are formed together interconnecting share common ground while connected Both bulk silicon-on-insulator embodiments provided. represent function, area 2F 2 needed per bit logic, where F minimum lithographic feature size.