作者: Saman Hosseini Hemeati , Saeed Gholami , Saeed Roshani , Sobhan Roshani
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摘要: In this paper, a new low-power SARADC is presented. the presented design, frequency dependency of power rather than conventional supply voltage emphasized. Our evaluations show that when mixed signal system drops down, ratio consumption in analog and digital units have different patterns. respect, for our target study share about constant while sections rapidly reduced. This means to lower total power, section must be optimized. study, has major unit as comparator. The design selected range 50 KHz - 200 KHz, which operations ADC Wireless Sensor Network (WSN) nodes. 6bit reported here consumes only 4.96 µW at 100 KHz. Ultra low makes suitable WSN node applications. proposed designed simulated 90nm CMOS 1v voltage.