Realization of a silicon nanowire vertical surround-gate field-effect transistor.

摘要: Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well technology. A variety of technical applications, such parts sensors, electronic photonic devices already been demonstrated. In particular, applications come more into focus, the ongoing miniaturization in microelectronics demands new innovative solutions. nanowires, particular epitaxially grown silicon (Si) are considered promising candidates post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to potential compatibility with existing CMOS One major advantage vapor–liquid– solid(VLS-) compared top-down fabricated is that well-defined surfaces. This reduces surface scattering, an issue which becomes important on nanoscale. Moreover, circumvent problem handling positioning nanometer-sized objects arises conventional pick-and-place approach, where by manipulating horizontally lying VLS-grown nanowires. The first step towards a realization nanowire element design manufacturing transistor. epitaxial growth vertical offers advantages over other approaches: For example, transistor gate can be wrapped around vertically oriented nanowire. Such wrapped-around allows better electrostatic control conducting channel drive current per device area than possible planar architecture. this Communication, generic process fabricating surround-gate field-effect (VS-FET) based described. Exemplarily, we used Si present characterization proving feasibility developed functionality device. Figure 1a shows schematic cross section through p-type MOSFET. device, inversion created close applying negative voltage. forms connects p-doped regions between source drain contacts electrically. Using concept, VS-FET would ideally require n-doped region elsewhere. Unfortunately, p-n-p structure abrupt transitions appears difficult realize if means vapor–liquid–solid mechanism using gold catalyst. difficulty here dopant atoms, dissolved catalyst droplet, might act reservoir, thus creating graded transition when switching another dopant. Therefore, consisting substrate (see 1b). If gate–drain gate–source distances not too long, it electrostatically still create along length entire wire. proposed configuration, p–n junction at contact (Figure 1a) replaced Au/n-Si Schottky tip. order investigate influence (current–voltage) I–V characteristics, array n-type (111)-oriented was imbedded spin-coated SiO2 matrix. After removing thin coverage from Au tips short reactive ion etching, 0.6 mm size were defined evaporating aluminum onto sample, approximately 10 contacted parallel. temperature-dependent measurements (shown 2) performed voltage substrate, while Al top held constant potential. reveal strong rectifying behavior thermally activated possessing activation energy eV. explained dominating behavior. fact forward-biased voltages furthermore proves that, expected, electrons majority charge carries. 1. Schematics a) p-channel MOSFET b)