Variable salicide block for resistance equalization in an array

摘要: The present invention facilitates memory devices and operation of dual bit single by providing systems methods that employ a salicide block to vary equalize the resistance array during fabrication. includes utilizing common charge dissipation region mitigate charge-loss protection against charging up various lines as result further plasma etching processes. equalizes in each wordline path with varied amount addition total resistance. Because provided otherwise varies depending on discharge element, for equalization provides greater reliability predictability processing. Other such shapes conducive any desired fall within scope invention.