Methods of forming electrical interconnects on semiconductor substrates

作者: Si-Young Choi , Bong-Young Yoo

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摘要: Methods of forming electrical interconnects on semiconductor substrates include the steps a first electrically insulating layer (e.g., silicon dioxide) and then contact hole in to expose underlying layer. A conductive region W, Ti, Tin, Al) is formed hole. step performed remove portion define recess therein which preferably surrounds an upper region. second Al, Cu, Ta Co) recess. Here, chosen have good coverage capability fully bury very low resistance even if some degree sacrificed. Planarization (e.g, CMP, etch-back) may also be surrounding Barrier metal layers conformable deposited prior therein.

参考文章(14)
Tetsuya Yagi, Takuji Sonoda, Nobuyuki Kasai, Shinichi Sakamoto, Method of making a mushroom-shaped gate electrode of semiconductor device ,(1993)
Carlos A. Mazure, Jon T. Fitch, Keith E. Witek, Method of formation of vertical transistor ,(1992)
Rich Klein, Ming-Ren Lin, Steven Avanzino, Scott D. Luning, Subhash Gupta, Dual damascene with a protective mask for via etching ,(1995)
Subhash Gupta, Rich Klein, Ming-Ren Lin, Steven Avanzino, Scott D. Luning, Self aligned via dual damascene ,(1996)
Donald S. Gardner, Xiao-Chun Mu, David B. Fraser, Srinivasan Sivaram, Methods of forming an interconnect on a semiconductor substrate ,(1992)
Ming-Ren Lin, Mark Chang, Richard J. Huang, Robin Cheung, Angela Hui, Simplified dual damascene process for multilevel metallization and interconnection structure ,(1995)
Kazuo Hayashi, Takuji Sonoda, Shinichi Sakamoto, Method of producing a semiconductor device including a Schottky gate ,(1989)