作者: Muniba Ahmad
DOI: 10.1109/INTELSE.2016.7475136
关键词:
摘要: A heterojunction PIN Diode in which an intrinsic layer (I-layer) of In0.53Ga0.47As is sandwiched between N-layer In0.52Al0.48As and p-layer modelled investigated using TCAD simulation. At all ternary uniformly doped epitaxial growth assumed for layers with abrupt interfaces. Since the design I-layer most critical diode operations, thickness varied simulation to calculate maximum leakage current breakdown voltage reverse bias operation, turn on at forward operation. By optimizing structure I-layer, we have demonstrated improved DC characteristics device. S-parameters are then calculated discussed a Single Pole Throw (SPST) switch configuration Diode.