The impact of classical electronics constraints on a solid-state logical qubit memory

摘要: AbstractWe describe a fault-tolerant memory for an error-corrected logical qubit based on silicondouble quantum dot physical qubits. Our design accounts constraints imposed by supportingclassical electronics. A signi cant consequence of the is to add error-prone idle stepsfor Even using schedule with provably minimum time, our noisemodel and choice error-correction code, we nd that these additional idles negate any bene tsof error correction. Using operations, can greatly suppress idle-inducederrors, making correction cial, provided operations achieve rateless than 2 10 5 . We discuss other consequences such as error-correctioncode operation speed. While analysis speci c this memoryarchitecture, methods develop are general enough apply architectures well.1 Introduction Quantum information processing (QIP) promises path towards resolving currently computationally-intractable problems [1]. However, bits (qubits) used storing are,unfortunately, much more susceptible errors classical bits. Realization error-correctedquantum computation, therefore, represents critical QIP engineering pursuit. key concept inthis pursuit redundant encoding in state many Thisredundancy allows one check correct them.This paper presents solid-state architecture single accountsfor both electronics native gate set|the available set transformations system provides. Quantum-computingarchitectures have been considered previously, example ion traps [2] [3,4].These analyses began study incorporating realistic implementation constraints. extendthese studies include explicit electronic constraints, where expect electronicsintegration be easier least constrained. From gained number