Strategies for branch target buffers

摘要: Achieving high instruction issue rates depends on the ability to dynamically predict branches. We compare two schemes for dynamic branch prediction: a separate target buffer and an cache based buffer. For caches of 4KB greater, prediction performance is strong function line size, weak size. An with size 8 (or 4) instructions performs about as well structure which has 64 256, respectively) entries. Software can rearrange basic blocks in procedure reduce number taken branches, thus reducing amount hardware needed. With software assistance, predicting all branches not branching 4 entry without assistance 32 assistance. The also benefits from software, but only sizes more than instructions.