Method for forming multileves interconnections for semiconductor fabrication
作者： Chien Chiang , David B. Fraser
DOI:
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摘要: A method for forming interconnections semiconductor fabrication and devices have such are described. first patterned dielectric layer is formed over a substrate has opening filled with conductive material. Another the second at least portion of The may serve as an etch-stop in patterning other layer. Also, be material before been formed. This exposes exposed removed.
lens.org 参考文章(45)
Robert R. Joseph, Man-Chong Wong, Composite insulator structure ,(1983)
Arthur M. Wilson, Clyde R. Fuller, Prabhakar B. Ghate, Maximum density interconnections for large scale integrated circuits ,(1977)
Evan Colgan, James W. Mayer, Jian Li, Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits ,(1991)
Peter S. Gwozdz, Method for interconnecting metallic layers. ,(1984)
Robbie W. Skinner, Joseph B. Delaney, Clyde R. Fuller, Semiconductor circuit having metallization with TiW ,(1987)
Trung T. Doan, Method of etching back of tungsten layers on semiconductor wafers, and solution therefore ,(1990)
Charles L. Standley, William L. Guthrie, Carter W. Kaanta, John E. Cronin, Kathleen A. Perry, William J. Patrick, Barbara J. Luther, Melanie M. Chow, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias ,(1985)
Stanley Wolf, Richard N. Tauber, Silicon Processing for the VLSI Era ,(1986)
Carter W. Kaanta, James K. Paulsen, Michael A. Leach, William J. Cote, Via-filling and planarization technique ,(1988)