On the status of wafer-level metal integrity testing

作者: Michael J. Dion

DOI: 10.1016/0026-2714(93)90087-F

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摘要: Abstract Wafer-level metal integrity testing is very complex. Trade-offs with test time, stress temperature, structure, technique, and true understanding of the stress, are all involved discussed in this work. A discussion conventional electromigration execution issues provided as a prelude to highly accelerated last section. Much published work wafer-level EM used help describe trade-offs involved.

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