Through-substrate vias formed by bottom-up electroplating

作者: Robert Mihailovich , Alexandros Papavasiliou , Adam Young , Jeff Denatale

DOI:

关键词:

摘要: A method of forming void-free, high aspect ratio through-substrate vias by “bottom-up” electroplating. In one embodiment, the requires providing a substrate, dielectric layer on substrate's bottom side, at least perforation through layer, via hole substrate from its top side to and over perforations, an isolation sidewalls hole, metal seed electroplating such that all perforations are plugged, up plugs fill hole.

参考文章(18)
Shian-Jyh Lin, Shing-Hwa Renn, Through-substrate via and fabrication method thereof ,(2010)
Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe, Bottom-up plating of through-substrate vias ,(2012)
Robert E. Jones, Terry G. Sparks, Conductive via formation utilizing electroplating ,(2007)
Yann Pierre Roger Lamy, Freddy Roozeboom, Willem Frederik Adrianus Besling, Method of Plating Through Wafer Vias in a Wafer for 3D Packaging ,(2009)
Warren M. Farnworth, Nishant Sinha, Conductive through wafer vias ,(2003)
Eric Cornelis Egbertus Van Grunsven, Freddy Roozeboom, Maria Mathea Antonetta Burghoorn, Franciscus Hubertus Marie Sanders, Through-substrate via and redistribution layer with metal paste ,(2009)
Hans-Joachim Barth, Jens Pohl, Through substrate via semiconductor components ,(2007)