Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication

摘要: An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the devices. dielectric over The etched back prepare for deposition of additional layers. surface scanned by an atomic force microscope (AFM) gather data representing wafer roughness. evaluated computer generate at least one roughness signal. Depending value signal, IC continues with next step, remedial action taken, adjusted subsequent wafers, or discarded.