Fault isolation of digital scan logic without ‘scan diagnosis’

作者: B. L. Yeoh , S. H. Goh , G. F. You , Hu Hao , Alan Tan

DOI: 10.1109/IPFA.2017.8060124

关键词:

摘要: Software scan diagnosis has been the de facto approach to narrow down possible defect locations in logic circuits by virtue of its speed and effectiveness. However, this capability is not supported for all product yield engineering custom electrical failure analysis naturally relied on. By approach, unless defects are gross, fault localization internal logical nodes can be challenging directly impacts ramp time-to-market. This paper describes demonstrates three effective methods leveraging pre-diagnostic test data a combination dynamic EFI techniques, as viable alternatives diagnosis. Case examples will presented.

参考文章(9)
S. H. Goh, B. L. Yeoh, G. F. You, Hu Hao, W. L. Sio, Jeffrey Lam, C. M. Chua, Fault isolation using Electrically-enhanced LADA (EeLADA) international symposium on the physical and failure analysis of integrated circuits. pp. 572- 576 ,(2015) , 10.1109/IPFA.2015.7224461
Ulrike Kindereit, Gary Woods, Jing Tian, Uwe Kerst, Rainer Leihkauf, Christian Boit, Quantitative Investigation of Laser Beam Modulation in Electrically Active Devices as Used in Laser Voltage Probing IEEE Transactions on Device and Materials Reliability. ,vol. 7, pp. 19- 30 ,(2007) , 10.1109/TDMR.2007.898074
S. H. Goh, G. F. You, B. L. Yeoh, Hu Hao, N. L. Chung, C. P. Yap, Jeffrey Lam, Wafer-level fault isolation approach to debug integrated circuits JTAG failures international symposium on the physical and failure analysis of integrated circuits. pp. 30- 34 ,(2014) , 10.1109/IPFA.2014.6898176
Venkat Krishnan Ravikumar, Winson Lua, Seah Yi Xuan, Gopinath Ranganathan, Angeline Phoa, Combinational Logic Analysis using Laser Voltage Probing ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis. pp. 35- 41 ,(2015) , 10.31399/ASM.CP.ISTFA2015P0035
Yan Pan, Atul Chittora, Kannan Sekar, Goh Szu Huat, You Guo Feng, Avinash Viswanatha, Jeffrey Lam, Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis. pp. 602- 607 ,(2013) , 10.31399/ASM.CP.ISTFA2013P0602
Winson Lua, Gopinath Ranganathan, Venkat Krishnan Ravikumar, Angeline Phoa, Combinational logic analysis case studies using laser voltage probing international symposium on the physical and failure analysis of integrated circuits. pp. 51- 54 ,(2016) , 10.1109/IPFA.2016.7564246
Venkat Krishnan Ravikumar, Understanding testing for dynamic fault isolation of microprocessors international symposium on the physical and failure analysis of integrated circuits. pp. 17- 21 ,(2016) , 10.1109/IPFA.2016.7564238
M. Lee, B.L. Yeoh, S.H. Goh, G.F. You, Alan Tan, Hu Hao, Y.H. Chan, Lin Zhao, Varun Gupta, H.H.W.T. Ma, S.P. Neo, G.B. Ang, Y.T. Ngow, Jeffrey Lam, C.C. Tay, Optimization of EeLADA for Circuit Logic Defect Localization Using Defect Simulation ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis. ,(2016) , 10.31399/ASM.CP.ISTFA2016P0540
Jayanth Mekkoth, Murali Krishna, Jun Qian, Will Hsu, Chien-Hui Chen, Yuan-Shih Chen, Nagesh Tamarapalli, Wu-Tung Cheng, Jan Tofte, Martin Keim, None, Yield Learning with Layout-aware Advanced Scan Diagnosis ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis. ,(2006) , 10.31399/ASM.CP.ISTFA2006P0412