作者: B. L. Yeoh , S. H. Goh , G. F. You , Hu Hao , Alan Tan
DOI: 10.1109/IPFA.2017.8060124
关键词:
摘要: Software scan diagnosis has been the de facto approach to narrow down possible defect locations in logic circuits by virtue of its speed and effectiveness. However, this capability is not supported for all product yield engineering custom electrical failure analysis naturally relied on. By approach, unless defects are gross, fault localization internal logical nodes can be challenging directly impacts ramp time-to-market. This paper describes demonstrates three effective methods leveraging pre-diagnostic test data a combination dynamic EFI techniques, as viable alternatives diagnosis. Case examples will presented.